This invention relates to the design, layout, testing and manufacture of microelectronic circuits and systems, and more particularly to apparatus and methods for verifying microelectronic circuits and systems prior to manufacture.
Present day ultra-large-scale integration (ULSI) circuits may include hundreds of thousands or millions of interconnected active electronic devices on an integrated circuit chip. The large capital investment required to fabricate and test large scale integrated circuits prior to sale to a customer and the difficulty, expense and loss of goodwill associated with reworking and replacing integrated circuits which fail to operate as planned, have increased the need to accurately characterize the electrical behavior of integrated circuits prior to their manufacture.
Moreover, now that submicron and deep-submicron (0.5 xcexcm and below) technologies have begun to dominate silicon chip manufacturing and the prospect of million-plus-gate chips operating at clock rates of 100 MHZ has become a reality, fundamental changes have had to be made to conventional integrated circuit design methodologies and the electronic design automation (EDA) tools based thereon. To meet the challenges posed by such large-scale circuits, techniques have been developed to represent integrated circuit designs at various levels of abstraction. According to these techniques, an integrated circuit design may be represented by an electrical schematic containing devices and nets interconnecting the devices and by geometric layout data that describes patterns of regions or elements to be formed in and/or on an integrated circuit substrate (e.g., wafer).
Techniques for managing highly integrated circuit designs include hierarchical design techniques. Using such techniques, a particular design is partitioned into functional cells and cells-within-cells, etc., so that at a given level of hierarchy the design may be analyzed as a set of cells and their respective interconnections, without being concerned with all the details of the contents of the cells (e.g., subcells within each cell).
These hierarchical techniques can be essential to the efficient performance of computer-assisted integrated circuit design verification. Such verification may include operations to perform layout versus schematic comparison (LVS) using computer-based design tools. As will be understood by those skilled in the art, tools to perform layout versus schematic comparison may include extraction software to extract a layout netlist from geometric layout data. An extracted layout netlist is then compared to an electrical schematic netlist to determine functional equivalence between the original integrated circuit schematic and the integrated circuit layout. One difficulty associated with the performance of these operations may be caused by a dissimilarity in the labeling of nets and devices in the extracted layout netlist relative to the electrical schematic netlist.
Conventional methods for determining correspondence between an electrical schematic netlist and a layout netlist are described in U.S. Pat. Nos. 5,249,133 to Batra entitled xe2x80x9cMethod for the Hierarchical Comparison of Schematics and Layouts of Electronic Componentsxe2x80x9d; U.S. Pat. No. 5,463,561 to Razdan entitled xe2x80x9cHigh Capacity Netlist Comparisonxe2x80x9d; and U.S. Pat. No. 5,243,538 to Okuzawa et al. entitled xe2x80x9cComparison and Verification System for Logic Circuits and Method Thereof.xe2x80x9d Another conventional method for determining correspondence includes operations to represent the electrical schematic netlist and the layout netlist as a schematic graph and a layout graph, respectively. Each of these graphs may be represented as bipartite graphs having vertices (also referred to herein as xe2x80x9cnodesxe2x80x9d) that represent devices and nets within their respective netlists. LVS software is then used to determine an isomorphism between the bipartite graphs.
The unambiguous determination of isomorphism between two arbitrary graphs may be a computationally intractable problem. To address this problem, heuristic methods for identifying graph isomorphisms with acceptable reliability and efficiency for ULSI designs have been developed. One generally established heuristic method is an iterative graph-coloring method described in articles by C. Ebeling and O. Zajicek entitled xe2x80x9cValidating VLSI Circuit Layout By Wirelist Comparison,xe2x80x9d Proceedings of ICCAD, pp. 172-173 (1983); and by C. Ebeling entitled xe2x80x9cGemini II: A Second Generation Layout Validation Program,xe2x80x9d IEEE ICCAD-88, Digest of Technical Papers, pp. 322-325, Nov. 7-10, (1988), the disclosures of which are hereby incorporated herein by reference. As described in these articles, an integer node value (color) is assigned to each node of a bipartite graph of the electrical schematic netlist and the extracted layout netlist, based on a graph invariant such as xe2x80x9cnumber of nearest neighborsxe2x80x9d (i.e., number of adjacent nodes/vertices). Each node is iteratively recolored as a function of the colors of its neighbors, until the maximum number of unique colors is achieved (i.e., an equilibrium state is achieved). Because these operations are independent of labeling, equivalent schematic and layout netlists generally will be represented by the same set of colors. A one-to-one correspondence may then be achieved by simply matching up each node in the schematic graph with a node in the layout graph that has the same color.
Unfortunately, some circuits may exhibit symmetry that may cause different nodes to receive the same color because the xe2x80x9cneighborhoodsxe2x80x9d associated with these nodes are similar. When two or more nodes have the same color, ambiguities in selecting matching nodes may arise. Typically, this situation is handled by making a guess as to which ones of the nodes in the schematic graph correspond to the same colored nodes in the layout graph, then assigning new colors to the matched nodes and then recoloring. If the guess was incorrect, a number of nodes may fail to match when the matching is applied at the next level of hierarchy, even though an alternate guess might have resulted in a complete one-to-one mapping.
For example, the AND-OR-INVERT (AOI) cell of FIG. 1 exhibits a number of symmetries with respect to input A because input A may be independently swapped with input B or input A may be swapped with input C if and only if input B is also swapped with input D. Similar symmetries also exist with respect to inputs B, C and D. FIG. 2 illustrates an original electrical schematic (S1) of the AOI cell and an extracted layout schematic (L1) of the AOI cell. FIG. 3 illustrates an original electrical schematic (S2) which contains the AOI cell S1 of FIG. 2 as a child cell and an extracted layout schematic (L2) which contains the AOI cell L1 of FIG. 2 as a child cell. As will be understood by those skilled in the art, verification of the schematics of FIG. 3 will only be concerned with the mapping of ports (W,X,Y,Z) of the AOI cell L1 of FIG. 2 to the ports (Q,R,S,T) of the schematic S2 of FIG. 2. However, because the symmetry of the design may cause the ports of each AOI child cell in FIG. 2 to acquire the same color when the schematic and layout graphs of the AOI child cells have been colored to an equilibrium state, a conventional LVS tool may make an arbitrary mapping which may be incorrect (e.g., Qxe2x86x92W, Rxe2x86x92Y, Sxe2x86x92X, Txe2x86x92Z). A consequence of this arbitrary mapping may be manifested at the next level of hierarchy.
For example, as illustrated by FIG. 3, an incorrect choice in the mapping of S1 to L1 (i.e., the child cells) may cause S2 and L2 (i.e., the parent cells) to be reported as nonequivalent after a coloring algorithm has been performed on the schematic and layout graphs at the parent level. Here, devices D1-D4 are distinct devices that are connected between the ports of the AOI xe2x80x9cchildxe2x80x9d cell and the ports of the xe2x80x9cparentxe2x80x9d cell. Thus, LVS software may report a mismatch between an original electrical schematic netlist and an extracted layout netlist, even though it is possible to make assignments among symmetric nodes that will result in a match. Typically, a consequence of this limitation in LVS software is that the software user must manually intervene by providing the LVS software with specific assignments to resolve ambiguities due to symmetry. Since it is not always clear where an erroneous guess was made, such manual intervention may be time consuming. For large and highly symmetric designs such as memories and gate arrays, these limitations may significantly reduce the utility of conventional LVS tools including hierarchical LVS tools using general-purpose graph isomorphism algorithms. In particular, the high degree of symmetry associated with large memories may force numerous arbitrary matchings or guesses to be made between layout and schematic. These guesses may preclude matching in the parent cells of the memories if the parent cells use permutations of the memory ports that are valid by virtue of the symmetries, but are inconsistent with the guesses.
To address some of these limitations associated with conventional verification tools, an LVS software tool 100 has been developed to determine equivalency between an integrated circuit schematic and an integrated circuit layout, using the operations 102-114 illustrated by the flow diagram of FIG. 4. This LVS software tool may be embodied in a commercially available product from the assignee of the present application, Avant! Corporation of Fremont, Calif. This software product, which is marketed under the tradename Hercules(trademark), is more fully described in an instruction manual by the same name, Release 2. Jan. 1, (1997), the disclosure of which is hereby incorporated herein by reference. In particular, the LVS software tool of FIG. 4 can perform the operations of generating a hierarchical electrical schematic netlist having at least one parent cell and a plurality of child cells in the parent cell, Block 102, and extracting a corresponding integrated circuit layout as a hierarchical layout netlist, Block 104. An operation is also performed to generate at least one color symmetrizing matrix corresponding to a child cell in the schematic netlist, Block 106. Here, the child cell may have a number of symmetries which, when taken alone or in combination, may result in a number of electrically equivalent permutations of the child cell. As illustrated by Block 108, operations are then performed to generate schematic and layout graphs of the parent cells in the schematic and layout netlists, respectively. These graphs are similar to the above-described bipartite graphs. The nodes in the schematic graph are then colored and a first color symmetry vector is generated for a child cell in the schematic graph. Similarly, the nodes in the layout graph are colored and a second color symmetry vector is generated for a child cell in the layout graph, Block 110.
An operation is then performed to determine an equivalency between the colors of the nodes in the schematic and layout graphs based on a selected permutation of the child cell in the layout graph, Block 112, and then an operation is performed to determine a vector equivalency between a product of the color symmetrizing matrix and the first color vector and a product of the color symmetrizing matrix and the second color vector, Block 114. Finally, a membership test is automatically performed at Block 116 to determine whether the selected permutation of the child cell can be derived from the valid symmetries associated with that child cell. As described in a textbook authored by G. Butler, entitled Fundamental Algorithms for Permutation Groups, Springer-Verlag, p. 144 (1991), a Furst-Hopcroft-Luks version of a Schreier-Sims method may be performed. Unfortunately, although the software tool of FIG. 4 typically requires no human intervention and works well with most designs exhibiting symmetry, the automatic performance of membership test to validate the accuracy of the matched layout and schematic may incur an unduly large computational expense and limit the applicability of the above software to large integrated circuit designs having large degrees of symmetry.
Thus, notwithstanding the above described attempts, there continues to be a need to provide verification tools which have the capability of automatically resolving ambiguities in symmetric circuits. Such tools should be conservative in the identification of graph isomorphism, in the sense that if any ambiguities remain after the verification operations are performed, a nonisomorphism result should be generated and the circuits should be designated as non-equivalent even if they may be equivalent. This is because the penalty for erroneously identifying equivalent circuits as nonequivalent (i.e., manual intervention by the user) is far less onerous than the penalty for misidentifying non-equivalent circuits as equivalent (i.e., the expense of prototyping and manufacturing an incorrect design).
It is therefore an object of the present invention to provide improved methods, apparatus and computer program products that can perform post-layout verification of microelectronic integrated circuits.
It is also an object of the present invention to provide improved methods, apparatus and computer program products that can perform layout versus schematic comparison of integrated circuits.
It is another object of the present invention to provide methods, apparatus and computer program products that can perform layout versus schematic comparison of hierarchical integrated circuits having symmetrical cells therein.
These and other objects, features and advantages can be provided, according to embodiments of the present invention, by preferred methods, apparatus and computer program products for determining equivalency between integrated circuit schematics and integrated circuit layouts. These methods, apparatus and computer program products are particularly useful as layout versus schematic (LVS) comparison tools when handling hierarchical designs that exhibit high degrees of overall symmetry and/or have large numbers of cells therein having symmetrical properties. These LVS tools preferably perform the operations of coloring a graph of an integrated circuit to an equilibrium state and then identifying a xe2x80x9cprovisionalxe2x80x9d swap group of nodes having the same color within the colored graph. The colored graph may be a colored layout graph or a colored schematic graph of the integrated circuit. The colored graph may be a colored bipartite graph having both net and device nodes therein. This xe2x80x9cprovisionalxe2x80x9d swap group of nodes corresponds to pins of a device that may be swappable by virtue of the fact that the nodes associated with the pins have the same color after a graph coloring operation has been performed. A new (e.g., unique) color is then assigned to a node within the identified swap group. An operation is then performed to recolor the layout graph (with the new colored node) until another equilibrium state has been achieved. During this recoloring operation, the node receiving the assigned color may be held at the assigned color. This recoloring operation may include operations to repeatedly partition nets and devices in alternating sequence until an equilibrium colored state is achieved. At this point, a determination of whether the swap group of nodes are independently swappable can be made by evaluating whether all the nodes within the swap group, with the exception of the node that received the assigned color, have the same color. If they do, then all the nodes in the swap group can be treated as independently swappable nodes.
Preferred embodiments of LVS comparison tools may also perform an operation of identifying at least one connected group within the swap group. This operation preferably comprises determining a first connected group of nodes as nodes within the swap group that are linked together (and to the node receiving the assigned color) by other nodes that have non-unique colors within the graph. Then, after the graph has been recolored to an equilibrium state, an operation can be performed to determine whether the nodes within the first connected group that did not received the assigned color all have the same color. If so, these nodes within the first connected group can be treated as being independently swappable (i.e., as their own swap group), even if all the nodes within the xe2x80x9cprovisionalxe2x80x9d swap group are not independently swappable.
Once nodes that belong to respective connected groups have been identified, subsequent or concurrent operations may also be performed to generate a first vector of first colors corresponding to a first swap group of nodes associated with a first child cell in an integrated circuit schematic graph having symmetric pins that include independently swappable pins and dependently swappable pins. Operations may also be performed to generate a second vector of second colors corresponding to a second swap group of nodes associated with a second child cell in an integrated circuit layout graph. These graphs may be graphs of first and second parent cells containing the first and second child cells, respectively, and nets connected to input nodes of the respective child cells. To resolve symmetries identified by the presence of duplicate colors within the first and second vectors, an assignment of a new color is made to a node within the first swap group of nodes in the schematic graph and a corresponding assignment is made to a node within the second swap group of nodes in the layout graph. This new color is preferably a unique color that is not within the first vector. This assignment of a new color to a node of a child cell is, when viewed at the parent level, actually an assignment of a color to a net that may be connected to one or more pins of a child cell(s). At the parent level, this net may be treated as a single node of the graph having a single color and each pin of a child cell that is connected to the net may be treated herein as having an effective xe2x80x9ccolorxe2x80x9d equal to the color of the net. Operations are then performed to generate a third vector of third colors corresponding to the first swap group by determining a new color for one of the nodes within the first swap group using a coloring operation that is a function of a device value of the first child cell and a color of another node in the first swap group. A fourth vector of fourth colors corresponding to the second swap group are also generated by determining a new color for one of the nodes within the second swap group using a coloring operation that is a function of a device value of the second child cell and a color of another node in the second swap group.
In particular, an embodiment of the operation to generate a third vector includes generating a new color for a first node in the first swap group using a coloring operation that is a function of a device value of the first child cell and a respective color of each of the other nodes in the first swap group. To reduce computational expense, this node/pin coloring operation is independent of the colors of nodes that are dependently swappable with the first node. Similarly, the operation to generate a fourth vector includes generating a new color for a second node within the second swap group using a coloring operation that is a function of a device value of the second child cell and a respective color of each of the other nodes in the second swap group. Again, to reduce computational expense, this node coloring operation is independent of the colors of nodes that are dependently swappable with the second node. More preferably, the operation to generate a third vector comprises generating a new color for a node within the first swap group using the following relationship: New Color=Existing Node Colorxe2x88x92(Device Value)xc3x97(xcexa3 Colors of Other Nodes in Respective Swap Group). An identical relationship is also preferably used to generate a fourth vector.
Preferred coloring operations performed by LVS tools of the present invention may also include initially determining a first vector of first colors corresponding to a first swap group of nodes associated with a child cell in an integrated circuit layout graph and then assigning a unique node color not within the first vector of colors to a first node within the first swap group. Operations are then performed to generate a second vector of colors corresponding to the first swap group by generating a new color for the first node using the following relationship: New Color=Unique Node Colorxe2x88x92(Device Value of Child Cell)xc3x97(xcexa3 Colors of Other Nodes in the First Swap Group). Preferably, this relationship does not require the computational expense associated with conventional operations to generate a product of a color symmetrizing matrix and a vector of node colors for a child cell.
Operations to perform layout versus schematic comparison may also include operations to color a schematic graph of a parent cell to an equilibrium state and then recolor nets connected to first and second child cells having the same device value. The operation to recolor the nets preferably uses a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Operations are then performed to generate distinct device values for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins. These operations to determine distinct device values are preferably performed in order to prevent an incorrect mapping of these child cells in the schematic and layout during subsequent device coloring operations. These operations preferably include determining a new device color for one cell (e.g., AOI cell) in the schematic by evaluating a product of the symmetric pin colors. In particular, the new device value for the child cell can be determined using the following relationship: New Device Value=Old Device Value+Π(Colors of Symmetric Pins of Cell). Alternatively, the new device value may be determined as the product of the colors of the symmetric pins. As determined by the inventors herein, merely determining an algebraic sum of the colors of the symmetric pins may not distinguish the AOI cells during subsequent coloring operations.
Still further embodiments of the present invention include operations to perform layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell. This tracing operation preferably comprises tracing a netlist path extending from the first device to a first bit line or a first word line electrically connected to the first memory cell. This netlist path may include a path defined by one or more nets and devices connected together and preferably connected between the first device and the first bit line (or first word line). The first bit line and/or first word line is then traced locally to identify a plurality of additional memory cells electrically coupled thereto along a column or row. Additional bit lines and words lines that are connected to these identified memory cells can also be traced in a similar manner to identify a plurality of rows and columns of memory cells in a memory array block.
Operations are also performed to determine one-to-one correspondence between an integrated circuit schematic netlist and the integrated circuit layout netlist by treating the plurality of identified memory cells in the layout netlist as a memory array block (or child cell containing a memory array block) and treating the bit lines and word lines as input pins to the block memory array that may be independently swappable. In particular, the words lines are typically independently swappable and the bit lines may be independently swappable as a group or independently swappable in pairs with each pair including a true and complementary bit line (BL, BLB).
The operations to trace the first bit line or the first word line may include tracing a first word line electrically coupled to the first memory cell to identify a first row of memory cells and then tracing a second bit line electrically coupled to a second memory cell in the first row of memory cells to identify a first column of memory cells. Alternatively, the operations to trace the first bit line or the first word line may include tracing a first word line electrically coupled to the first memory cell to identify a first row of memory cells and then tracing the first bit line electrically coupled to the first memory cell to identify a first column of memory cells. Bit lines and word lines connected to other memory cells in the identified rows and columns may also be traced.
In the event the integrated circuit comprises SRAM cells, the operation to scan the layout netlist may include scanning devices in the layout to identify a first field effect transistor having a gate electrode electrically connected to a source/drain region of a second field effect transistor. The scanning operation may then be continued by scanning the second field effect transistor to determine if a gate electrode of the second field effect transistor is electrically connected to a source/drain region of the first field effect transistor. Identification of the device as an SRAM bit cell is at least preliminarily confirmed if both these conditions are met. Alternatively, in the event the integrated circuit comprises DRAM cells, the step of scanning a layout netlist of the integrated circuit comprises scanning devices in the plurality of memory cells and in the plurality of non-memory cells to identify a first access transistor having a source/drain region electrically connected to an electrode of a storage capacitor. This identification at least preliminarily confirms the device as a DRAM bit cell. Subsequent local tracing operations about and around the identifiable characteristic can then be performed to confirm the identity of a memory bit cell.
Further operations to determine equivalency between an integrated circuit schematic and an integrated circuit layout containing a plurality of memory blocks therein arranged hierarchically using parent and child layout cells, may include translating word line and bit line connections from a first memory block within a child layout cell into a higher level parent layout cell containing the child layout cell and also scanning a layout netlist of the parent layout cell to identify a first device therein that has an identifiable characteristic associated with a plurality of memory cells relative to a plurality of non-memory cells within the integrated circuit layout. A layout netlist of a first memory cell containing the first device is then traced to identify a first bit line or a first word line therein that is electrically coupled to the first memory cell. This tracing operation may then continue with an operation to trace the first bit line and/or the first word line to identify a transistor level memory block within the parent layout cell. A preferred operation may then be performed to combine the transistor level memory block with the first memory block that was translated from the child cell to the parent cell.
Operations to determine equivalency may also include identifying a plurality of memory blocks defined by a respective plurality of child layout cells contained within a parent layout cell, using a depth-first search operation that identifies respective bit line and word line connections to the memory blocks. A layout netlist of the parent layout cell is then scanned to identify a first device therein that has an identifiable characteristic associated with a plurality of memory cells relative to a plurality of non-memory cells within the integrated circuit layout. This scanning operation is preferably followed by an operation to trace a layout netlist of a first memory cell containing the first device in order to identify a first bit line or a first word line therein that is electrically coupled to the first memory cell. Once this tracing operation has been performed, the identified first bit line or first word line may be traced in order to identify a transistor level memory block within the parent layout cell. The identified plurality of memory blocks may then be combined with the transistor level memory block within the parent layout cell.